1. Field of the Invention
The present invention generally relates to data-buffering technology in a data processing system. More specifically, the present invention relates to a buffer management device for improving buffer usage and reducing page-miss occurrences while accessing buffer devices in the system controller of a data processing system.
2. Description of the Related Art
Data buffering is a critical issue in modern data processing systems. Generally speaking, data-buffering techniques are used in two operation environments for improving the performance of data transmission. The first operation environment is where the source terminal and destination terminal operate at different operating speeds. An example is a communication system wherein the source terminal operates at a higher operating speed than the destination terminal. Therefore, the destination terminal needs enough buffer memory for buffering incoming data. The second operation environment is where there are many source devices but very few or only one destination device. For example, a system controller in a data processing system needs one or more buffer devices to effectively manipulate the data transfer between the connected devices.
FIG. 1 (Prior Art) illustrates a block diagram of a portion of a conventional data processing system in the neighborhood of the system controller 20. As shown in FIG. 1, system controller 20 is connected, or coupled, to processor 10, display system 60, peripheral bus 32 and main memory 40. The functions of these components in the data processing system will be briefly described as follows.
Processor 10 is typically the processing center of the data processing system, and is used to receive instructions and sequentially execute them. During the execution period, processor 10 fetches required program or data code from storage media and returns an execution result. Main memory 40, usually implemented by Dynamic Random Access Memories (DRAMs), is typically the primary program/data source since it has a shorter access time than most other storage media except Static Random Access Memories (SRAMs). Peripheral bus 32 is used to bridge, or connect, other peripheral devices with the data processing system. Hereinafter, when discussing peripheral bus 32, it will be understood that the discussion equally applies to the devices connected to peripheral bus 32. Display system 40 is used to visually display the user interface of the data processing system. Traditionally, the display of display system 60 is established through a video card connected to peripheral bus 32. Modern data processing systems adopt a new architecture to directly couple display system 60 and system controller 20 for improving the display performance. Finally, system controller 20 is a bridge device for interfacing processor 10, display system 60, peripheral bus 32 and main memory 40, as shown in FIG. 1.
FIG. 1 also shows the typical buffer devices of system controller 20 for controlling data transfer between the connected components, including processor 10, display system 60 and peripheral bus 32, to a destination component, usually main memory 40. The buffer devices of system controller 20 shown in FIG. 1 comprise memory controller 201, processor buffer 203, display buffer 205, peripheral buffer 207 and buffer management circuit 209.
Processor buffer 203, display buffer 205 and peripheral buffer 207 are used to buffer incoming data or requests from processor 10, display system 60 and peripheral bus 32, respectively. Each of these buffers (203, 205, 207) can temporarily store several items of data. In addition, the operations of processor buffer 203, display buffer 205 and peripheral buffer 207 are controlled by buffer management circuit 209. Memory controller 201, which is responsible for physically accessing main memory 40, sequentially processes the data stored in these buffers. Briefly speaking, processor 10, display system 60 and peripheral bus 32 issue data to the corresponding buffer devices under the control of buffer management circuit 209. Then memory controller 201 performs the access operations for transferring the data stored in these buffer devices into main memory 40. It is clear that FIG. 1 only exhibits an example for transmitting data from several components (processor 10, display system 60 and peripheral bus 32) to main memory 40 and is not intended to limit the scope of the present invention.
Processor buffer 203, display buffer 205 and peripheral buffer 207 each typically include a number of memory blocks. Each of the memory blocks can buffer one data item, regardless of size. FIG. 2 (Prior Art) illustrates a schematic diagram of the internal structure of processor buffer 203 in a conventional data processing system. Processor buffer 203, as shown in FIG. 2 in simplified form, comprises four memory blocks, denoted by 203a, 203b, 203c and 203d, respectively. In addition, each memory block comprises thirty-two memory units, wherein each memory unit is equivalent to a byte in the present example. However, it is understood by those skilled in the art that the number of memory units contained in each memory block can be altered as desired for a particular application.
Memory blocks 203a, 203b, 203c and 203d temporarily store data contained in the request issued from processor 10. In FIG. 2, slashed portions in the memory blocks 203a-203d represent memory units containing stored data. Generally, memory controller 201 sequentially processes the data stored in these memory blocks. Furthermore, as shown in FIG. 2, there are four tag memories 209a-209d embedded in buffer management circuit 209 that are dedicated to memory blocks 203a-203d, respectively. These tag memories (209a, 209b, 209c and 209d) store addressing information of the data stored in the corresponding memory blocks (203a, 203b, 203c and 203d). Generally speaking, each tag memory stores the common bits of the addresses corresponding to each memory unit in the corresponding memory block.
Assume that a complete address for addressing any data stored in a memory block contains thirty-two bits in this example, namely, a.sub.31 :a.sub.0. Therefore, each of tag memories 209a-209d should at least store 27 bits, that is, a.sub.31 :a.sub.5, which are the common bits of the addresses for all memory units in the same memory block. The relationship between the addressing information stored in the tag memory and the data stored in the corresponding memory block can be explained by the following example. Assume that the addressing information stored in tag memory 209a is AF01A1[100]. The address notations are briefly described as follows. The addressing information "AF01A1", which is not enclosed by brackets, is in the hexadecimal format and corresponds to address bits a.sub.31 :a.sub.8 in this case. In addition, the addressing information "[100]", which is enclosed by brackets, is in the binary format and corresponds to address bits a.sub.7 :a.sub.5. According to the addressing information contained in tag memory 209a and the sequence of the memory units, the location of data (shaded in memory block 203a) temporarily stored in memory block 203a is identified. FIG. 3 (Prior Art) schematically illustrates the addressing mechanism in memory block 203a. According to the addressing mechanism shown in FIG. 3, the addresses for the data stored in memory block 203a are AF01A14A-AF01A14E.
However, it is evident that conventional buffer devices do not efficiently use buffer memory. In the conventional buffer, any data containing only one or a few bytes is still required to occupy one memory block, such as is shown regarding memory blocks 203b and 203c in FIG. 2. A conventional solution is to reduce the number of memory units contained in each memory block. For example, the number of memory units can be reduced to eight, thereby improving the memory usage of memory blocks like 203b and 203c in FIG. 2. However, this modification may complicate the handling processes for the data stored in memory block 203d.
In addition, the particular accessing mode, such as the page-hit access mode or page-miss access mode, has an influence on the memory access speed. Generally speaking, a page-hit access requires fewer processing cycles than a page-miss access does. For example, in a memory system operating at 100 MHz, a page-hit access requires about 5 clock cycles to be processed, whereas a page-miss access requires about 13 clock cycles to be processed. In fact, the data issued from the various sources, such as processor 10, display system 60 and peripheral bus 32, are random. Consequently, page-miss occurrences are quite high. Therefore, reducing page-miss occurrences is an approach to improving overall system performance.